U.S. Pat. No. 4,477,825, issued Oct. 16, 1984 to Yaron et al., describes a double-poly electrically erasable programmable read only memory (EEPROM) device that utilizes dual field effect transistors to control current flow through a channel region between source and drain regions. A floating gate, formed from a first layer of polycrystalline silicon, overlays the channel region. A control gate, formed from a second layer of polycrystalline silicon overlays the floating gate. To read the cell, the control gate is typically charged to draw electrons into the channel and to permit current flow. However, this effect may be blocked by the floating gate positioned between the channel and the control gate. The floating gate influences the current flow in the channel as a function of the charge trapped on the floating gate. This "double-poly" EEPROM cell is programmed by tunneling charge carriers on or off the floating gate with suitably applied electric fields that act across thin oxide layers; the size and thickness of the thin oxide layers are critically important to proper operation of the device.
The '825 Yaron et al. patent teaches a one-step etching process for locating and defining a thin oxide tunneling region. The borders of the oxide tunneling region are located interior to and displaced from the borders of both the encompassing field oxide layer and the edges of the overlaying gates. The polysilicon floating gate comprises two portions which are connected together by dual paths positioned on each side of the source to drain current path. One portion of the gate operates over the channel region as a memory transistor, while the other portion contains the tunneling region. The cell layout described in the Yaron et al. patent provides a high cell packing density and simultaneously segregates the thin oxide region from areas of objectionable mechanical and electrical stress. Also, the thin oxide is protected from future, edge degrading etching steps.
While double poly EEPROM cells provide a high density memory device and exhibit acceptable endurance, they are limited to use in commodity memory products and require a complex fabrication process.
EEPROM cells which utilize a single layer of polysilicon, on the other hand, while providing lower density than double poly cells, require a much simpler fabrication process and are suitable not only for memory devices, but also for logic and custom design applications.
Furthermore, "single-poly" EEPROM devices eliminate the inter-poly capacitance problem associated with double-poly devices. In a double-poly cell, to facilitate the double-poly structure, an oxide layer must be grown on the lower layer of polysilicon. Since only a weak oxide structure can be grown on polysilicon, double-poly devices exhibit leakage through the interpoly oxide layer. This leakage adversely effects device reliability. In a single-poly device, the dielectric oxide layer is grown on the semiconductor substrate, resulting in a strong, single-crystal oxide layer and elimination of the leakage problem associated with double-poly cells.
In a single poly device, both the floating gate and the control gate function are performed by a single polycrystalline silicon layer. In general, the floating gate function and the control gate function are performed by different areas of the single poly layer. For capacitive coupling between the floating gate and the control gate, which is used to transfer a switch voltage from the control gate to the floating gate so as to permit the write/erase operation of the floating gate, a thin tunnel-oxide MOS capacitor is generally used.
Examples of single poly EEPROM devices are disclosed by R. Cuppens, et al., "An EEPROM for Microprocessors and Custom Logic", SC-20 IEEE J. of Solid State Cir. 603 (1985); N. Matsukawa, et al., "A High Density Single-Poly Si Structure EEPROM with LB (Lower Barrier Height) Oxide for VLSI's", 1985 Symposium on VLSI Technology: and J. Miyamoto, et al., "High Performance Single Polysilicon EEPROM Cells". However, none of the single-poly cells disclosed in the above-referenced documents disclose a cell structure wherein the thin tunneling oxide regions are confined within the boundaries of the underlying drain region. Rather, in each of these cells, the edges of the thin tunneling oxide region are coincident either with a PN junction of the underlying drain region or with the boundary of an adjacent field oxide region, leading to the reliability problems discussed in the above-mentioned .div.852 Yaron et al. patent and larger cell size due to the larger effective tunnel oxide area.